臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

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	臺大學術典藏NTU Scholars

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Institution	Date	Title	Author
臺大學術典藏	1990-03	A New Method for Two-Dimensional VLSI Layout Compaction Design	Chen, H. F.; Hsiao, P, Y.; Feng, Wu-Shiung; Chen, Sao-Jie; Chen, H. F.; Hsiao, P, Y.; 馮武雄; 陳少傑; Feng, Wu-Shiung; Chen, Sao-Jie
臺大學術典藏	1990-03	An Alternating Router for Compacted Routing Area	Tsai, C. C.; Chen, Sao-Jie; Feng, Wu-Shiung; Tsai, C. C.; 陳少傑; 馮武雄; Chen, Sao-Jie; Feng, Wu-Shiung
臺大學術典藏	1990-03	Routing Techniques in Staircase Channels	Fang, S. C.; Chen, Sao-Jie; Feng, Wu-Shiung; Fang, S. C.; 陳少傑; 馮武雄; Fang, S. C.; Chen, Sao-Jie; Feng, Wu-Shiung
國立臺灣大學	1990	A Topological Sorting Algorithm for Three-Layer Channel Routing	Chang, K. E.; Lai, T. H.; 馮武雄; Chang, K. E.; Lai, T. H.; Feng, Wu-Shiung
國立臺灣大學	1990	An Application of an Expert System in Layout Compaction of VlSI Design	Hsiao, P. Y.; 馮武雄; Chen, H. F.; Hsiao, P. Y.; Feng, Wu-Shiung; Chen, H. F.
國立臺灣大學	1990	Generalized Terminal Connectivity Problem	Tsai, C. C.; Chen, S. J.; 馮武雄; Tsai, C. C.; Chen, S. J.; Feng, Wu-Shiung
國立臺灣大學	1990	New Algorithms Based on Multiple Storage Quadtrees in Hierarchical Compaction of VlSI Mask Layout	Hsiao, P. Y.; 馮武雄; Chen, H. F.; Hsiao, P. Y.; Feng, Wu-Shiung; Chen, H. F.
國立臺灣大學	1990	Using Multiple Storage Quad Tree on a Hierarchical VLSI Compaction Scheme	Hsiao, P. Y.; 馮武雄; Hsiao, P. Y.; Feng, Wu-Shiung
國立臺灣大學	1990	An Improved Analytical Model of Short Channel MOSFETs Suitable for Circuit Simulation	Chow, H. C.; Wang, J. H.; Kuo, J, B.; 馮武雄; Chow, H. C.; Wang, J. H.; Kuo, J, B.; Feng, Wu-Shiung
國立臺灣大學	1990	Optimal Aspect Ratios of Building Blocks for Floorplan Designs	Shih, P. H.; 馮武雄; Shih, P. H.; Feng, Wu-Shiung
國立臺灣大學	1990	Optimal Aspect Ratios of Building Blocks for Generally Structured VLSI Floorplan Design	Shih, P. H.; 馮武雄; Shih, P. H.; Feng, Wu-Shiung
國立臺灣大學	1990	Via Minimization with Associated Constraints in Three-Layer Routing Problem	Fang, S. C.; Chang, K. E.; 馮武雄; Fang, S. C.; Chang, K. E.; Feng, Wu-Shiung
國立臺灣大學	1990	Generalized terminal connectivity problem for multilayer layout scheme	Tsai, Chia-Chun; Chen, Sao-Jie; Feng, Wu-Shiung
國立臺灣大學	1989-12	An H-V Tile-Expansion Router	Tsai, C. C.; 陳少傑; 馮武雄; Tsai, C. C.; Chen, Sao-Jie; Feng, Wu-Shiung
臺大學術典藏	1989-12	An H-V Tile-Expansion Router	Tsai, C. C.; Chen, Sao-Jie; Feng, Wu-Shiung; Tsai, C. C.; 陳少傑; 馮武雄; Chen, Sao-Jie; Feng, Wu-Shiung
國立臺灣大學	1989-08	The Control Model for a Knowledge-Based Approach to VLSI Compaction Design	Chen, S. F. Steven; Hsiao, P. Y.; 馮武雄; Wang, W. T.; Dai, S. N.; Chen, S. F. Steven; Hsiao, P. Y.; Feng, Wu-Shiung; Wang, W. T.; Dai, S. N.
國立臺灣大學	1989-06	An Improved Control Strategy for Expert Compaction Design	Hsiao, P. Y.; Chen, H. F.; 馮武雄; Chen, S. J.; Tsai, C. C.; Hsiao, P. Y.; Chen, H. F.; Feng, Wu-Shiung; Chen, S. J.; Tsai, C. C.
國立臺灣大學	1989-06	An Improved Control Strategy for Expert Layout Compaction Design	Hsiao, P. Y.; Chen, H. F.; 馮武雄; 陳少傑; Tsai, C. C.; Hsiao, P. Y.; Chen, H. F.; Feng, Wu-Shiung; Chen, Sao-Jie; Tsai, C. C.
臺大學術典藏	1989-06	An Improved Control Strategy for Expert Layout Compaction Design	Chen, H. F.; 馮武雄; 陳少傑; Tsai, C. C.; Hsiao, P. Y.; Chen, H. F.; Feng, Wu-Shiung; Chen, Sao-Jie; Tsai, C. C.; Hsiao, P. Y.; Hsiao, P. Y.; Chen, H. F.; Feng, Wu-Shiung; Chen, Sao-Jie; Tsai, C. C.
國立臺灣大學	1989	A Novel Implementation of Pipelined Toeplitz System Solver	Jou, I. C.; Hu, Y. H.; 馮武雄; Jou, I. C.; Hu, Y. H.; Feng, Wu-Shiung
國立臺灣大學	1989	Constrained Via Minimization for Three-Layer Routing	Chang, K. E.; Jyu, H. F.; 馮武雄; Chang, K. E.; Jyu, H. F.; Feng, Wu-Shiung
國立臺灣大學	1989	Graph Contractibility Problem for VLSI Layer Assignment	Chang, K. E.; 馮武雄; Chang, K. E.; Feng, Wu-Shiung
國立臺灣大學	1989	Using Hierarchical Multiple Storage Quad Tree on a Constraint-Graph Layout Compaction	Hsiao, P. Y.; 馮武雄; Hsiao, P. Y.; Feng, Wu-Shiung
國立臺灣大學	1989	A Heuristic Scanning Line Approach for an Expert Layout Compactor	Hsiao, P. Y.; Chen, S. F. Steven; 馮武雄; Hsiao, P. Y.; Chen, S. F. Steven; Feng, Wu-Shiung
國立臺灣大學	1989	An Efficient Layer Assignment for Three-Layer Restrictive VLSI Routing	Chang, K. E.; Fang, S. C.; 馮武雄; Chang, K. E.; Fang, S. C.; Feng, Wu-Shiung

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